As complementary metal oxide semiconductor (CMOS) and other semiconductor technologies shrink in size, there are corresponding improvements in device capacity, bandwidth, and cost. Furthermore, as frequencies of devices and buses increase, the performance of electronics may also increase proportionally. However, shrinking process technologies and increasing frequencies also present challenges, often requiring designers to compensate for various undesirable side-effects.
As an example, as semiconductor processing technologies have improved, the interconnect traces that semiconductor device manufacturers use to interconnect components on integrated circuits have become much smaller in both width and depth. Because of this, such traces are often more resistive than in the past. Furthermore, smaller sizes and thinner oxide layers often increase the current leakage of transistor gates. These two factors combine to produce higher voltage drops along device interconnect traces. Such voltage drops can pose problems in many situations, including for example, reduced voltage margins and decreased signal integrity.
The increased density and higher operational frequencies of semiconductor devices also increase the coupling of noise from adjacent traces and device elements. Compounding these problems is the tendency of many newer devices to utilize lower signal voltages. Voltage drop and noise coupling become even more problematic in the face of such lower absolute and relative voltages. Furthermore, real-world devices in general suffer from manufacturing process imperfections and experience nominal voltage and temperature variations during operation.
Various forms of differential signaling are often used to address the problems mentioned above. In one form of differential signaling, often referred to as “pseudo-differential” signaling, a common reference voltage is distributed to multiple signal receivers. Signal voltages are then specified relative to the common reference voltage. Such signal voltages may be digital or analog in nature. Regardless, the multiple signal receivers interpret respective data signal voltages by comparing each of them to the common reference voltage to produce output signal voltages.
To reduce the effects of voltage drops and noise coupling, both a signal (such as a data signal) and its associated reference voltage may be given similar physical routings. Because of their similar routings, both the signal voltage and the reference voltage are subject to similar degrading influences (such as voltage drop and noise coupling), and the signal voltage therefore maintains a generally fixed—or at least proportional—relationship with the reference voltage.
Within a given integrated circuit, using similar physical routings for a signal and its associated reference voltage is effective to some degree, but it can be inadequate in devices where interconnect resistances are high and/or where there are large leakage currents. A typical individual physical routing has a resistance that increases as its length increases. A voltage drop over such a physical routing may be calculated as the product of the resistance and any leakage current produced by devices connected by way of the routing. As an example, the traces of a modern CMOS process might exhibit a resistance of 100 milli Ohms per micron of trace length. Leakage currents might be on the order of 200 nano Amps per square micron. Assuming a trace length of 1000 microns and a trace width of 0.33 microns, a typical interconnection scheme might produce a voltage drop of approximately 192 milli Volts between a nominal reference voltage and the “actual” reference voltage as it is received by various components, including “pseudo-differential” signal receivers.
Such a drop in actual reference voltage can result in significantly decreased margin or “headroom” between the actual reference voltage and ground. Also, as the reference voltage approaches ground, there is a concomitant reduction in the range of voltages that qualify as “low” in comparison to the reference voltage. Consequently, the circuitry exhibits increased sensitivity to noise. The problem is particularly acute in high-speed devices where even the nominal or ideal reference voltage value is relatively low. In devices such as these, any further lowering of the nominal reference voltage threatens to significantly impair device operation. Furthermore, as semiconductor process technologies continue to shrink and to operate at ever higher frequencies, and as operating voltages continue to decrease, these types of interconnect-related voltage drops will become even more significant.
When two integrated circuit (IC) chips are engaged in a communication, a signal may be transmitted from one chip and received at another chip. The signal may be a signal voltage that is transmitted over a channel between a transmitting chip and a receiving chip. In addition to voltage changes (such as voltage drops) that result from interconnect traces that are internal to a given IC chip that is receiving a data signal (i.e., those voltage changes within a receiving chip), voltage changes can result from effects internal to a transmitting chip and from effects of a channel that interconnect the transmitting and receiving chips. For example, channel DC resistance induces voltage errors in many current signaling systems. Because of channel DC resistance, a data signal can shift in voltage as it traverses a signaling channel. Consequently, the farther apart two chips are located on a given signaling channel, the greater the voltage swing reduction that is likely to occur because of increasing channel DC resistance that forms a voltage divider with termination resistance.
In short, data signaling voltages can be adversely affected by increasing and/or differing resistances and currents, by increasing frequencies, by noise corruption, etc. due to effects both internal to one or more chips and the data signaling channel therebetween. Taken individually, any one of these factors can result in data signaling errors. Collectively, these factors can severely impact the ability to properly detect received data signaling—especially if data signaling voltage changes and “actual” reference voltage changes occur in converging directions.